The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area.
As feature size continues to shrink in advanced semiconductor manufacturing process, conventional photolithography may not provide enough resolution for the desired pitch sizes. Multiple-patterning techniques, such as self-aligned double-patterning (SADP) and self-aligned quadruple patterning (SAQP), may be used to pattern mask layers with small pitch sizes. The mask layer patterns defined by multiple-patterning may need to be cut, e.g., when the patterned mask layer are used to form conductive features in subsequent processing. Cut masks are used to form the cut patterns. Challenges exist in the formation of cut masks. There is a need in the art for improved methods of forming cut masks.